By reverse biasing the gate of an N-CHANNEL JFET with respect to its Source, the width of depletion region increases considerably. This results the reduction of channel thickness, which further increases its resistance. And as a net result the Drain Current Id Reduces.

If the polarity gate voltage is reversed so as to apply a positive bias to the gate with respect to Source, the P-N Junctions between the gate and the channel would then be Forward biased. Since a Forward bias Reduces the width of Depletion region , the thickness of channel would increase with a corresponding decrease in channel resistance. As a result, Drain Current Id would increase beyond the JFETs Idss value.

The normal operation of a JFETs is in its Depletion mode. However it is Possible to increase or enhance the conductivity of JFET Channel. This increases the TRANSCONDUCTANCE gm.

As the name suggests, DEPLETION ENHANCEMENT MOSFET (DE-MOSFET) was developed to be used in either or both the DEPLETION and ENHANCEMENT Modes.


n channel depletion enhanced mosfet


Figure shows the construction of an N- Channel Depletion MOSFET. It consists of a highly doped P-type substrate into which two blocks of heavily doped N-type material are diffused forming the Source and Drain. An N-channel is formed by diffusion between the source and Drain.
The type of impurity for the channel is same as for the source and drain. Now a thin layer of SiO2 dielectric is grown over the entire surface and holes are cut through the SiO2 layer to make contact with the N-type blocks. metal is deposited through the holes to provide drain and source terminals, and on the surface area between drain and source, a metal plate is deposited.
This layer constitutes the Gate. SiO2 layer results an high Impedence about 10^10 to 10^15 ohms.

A P-channel DE-MOSFET is constructed just like an N-CHANNEL, starting with an N-type substrate and diffusing P-type drain and source blocks and connecting them internally by a P-dopped channel region.

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